Dual Data Accesses - Analog Devices ADSP-2106x SHARC User Manual

Both the core processor and I/O processor have access to the external bus
(DATA , ADDR ), via the ADSP-2106x's external port. The external
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port provides access to off-chip memory and peripherals; it can also access
the internal memory of other ADSP-2106xs connected in a multiprocessing
system. This busing scheme allows the ADSP-2106x to have a single
unified address space in which both code and data is stored.
External memory can be either 16, 32, or 48 bits wide; the ADSP-2106x's
DMA controller automatically packs external data into the appropriate
word width, either 48-bit instructions or 32-bit data.
Note that the ADSP-2106x's internal memory is divided into two blocks,
called Block 0 and Block 1, while the external memory space is divided
into four banks.
5.1.1

Dual Data Accesses

The ADSP-2100 and ADSP-21000 Family DSPs traditionally define
memory as either program memory, for instructions, or as data memory,
for data storage. The processors' modified Harvard architecture, however,
allows data storage within program memory. The ADSP-2106x retains the
ADSP-21000 Family's separate on-chip buses for program memory and
data memory, but does not pre-define the two on-chip memory blocks as
either PM or DM. This allows the memory to be freely configured to store
different combinations of code and data.
The independent PM and DM buses allow the ADSP-2106x's processor
core to simultaneously access instructions and data from both memory
blocks. If the core tries to access two words from the same memory block
(over the same bus) for a single instruction, however, an extra cycle is
needed. Instructions are fetched over the PM bus or from the instruction
cache. Data can be accessed over both the DM bus (using DAG1) and the
PM bus (using DAG2). Figure 5.1 shows the memory bus connections on
the ADSP-2106x.
The ADSP-2106x's two memory blocks can be configured to store different
combinations of 48-bit instruction words and 32-bit data words.
Maximum efficiency (i.e. single-cycle execution of dual-data-access
instructions), though, is achieved when one block contains a mix of
instructions and PM bus data while the other block contains DM bus data
only.
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