Analog Devices ADSP-2106x SHARC User Manual page 667

Control/Status Registers
#define GP1 0x6c /* DMA1 General purpose / 2-D DMA
#define DB1 0x6d /* DMA1 General purpose / 2-D DMA, not on 21061 */
#define DA1 0x6e /* DMA1 General purpose / 2-D DMA, not on 21061 */
#define II3 0x78 /* Internal DMA3 memory address
#define IM3 0x79 /* Internal DMA3 memory access modifier
#define C3 0x7a /* Contains number of DMA3 transfers remaining */
#define CP3 0x7b /* Points to next DMA3 parameters
#define GP3 0x7c /* DMA3 General purpose / 2-D DMA
#define DB3 0x7d /* DMA3 General purpose / 2-D DMA, not on 21061 */
#define DA3 0x7e /* DMA3 General purpose / 2-D DMA, not on 21061 */
/* LBUF0, LBUF1, LBUF2, LBUF4, LBUF5, LCTL, LCOM, LAR, LSRQ, LPATH1,
LPATH2, LPATH3, LPCNT, CNST1, and CNST2 reg's are not on the 21061 */
#define LBUF0 0xc0
#define LBUF1 0xc1
#define LBUF2 0xc2
#define LBUF3 0xc3
#define LBUF4 0xc4
#define LBUF5 0xc5
#define LCTL 0xc6
#define LCOM 0xc7
#define LAR 0xc8
#define LSRQ 0xc9
#define LPATH1 0xca
#define LPATH2 0xcb
#define LPATH3 0xcc
#define LPCNT 0xcd
#define CNST1 0xce
#define CNST2 0xcf
#define STCTL0 0xe0 /*SPORT0 Transmit Control Register
#define SRCTL0 0xe1 /*SPORT0 Receive
#define TX0 0xe2 /*SPORT0 Transmit Data Buffer
#define RX0 0xe3 /*SPORT0 Receive Data Buffer
#define TDIV0 0xe4 /*SPORT0 Transmit Divisor
#define TCNT0 0xe5 /*SPORT0 Transmit Count Reg
#define RDIV0 0xe6 /*SPORT0 Receive Divisor
#define RCNT0 0xe7 /*SPORT0 Receive Count Reg
#define MTCS0 0xe8 /*SPORT0 Multichannel Transmit Selector
#define MRCS0 0xe9 /*SPORT0 Multichannel Receive Selector
#define MTCCS0 0xea /*SPORT0 Multichannel Transmit Selector
#define MRCCS0 0xeb /*SPORT0 Multichannel Receive Selector
#define KEYWD0 0xec /*SPORT0 Receive Comparison, 21061 only
#define KEYMASK0 0xed /*SPORT0 Receive Comparison Mask, 21061 only */
#define SPATH0 0xee /*SPORT0 Path Length (MMP), not on 21061
#define SPCNT0 0xef /*SPORT0 Path Counter (MMP), not on 21061
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/* Link buffer 0
/* Link buffer 1
/* Link buffer 2
/* Link buffer 3
/* Link buffer 4
/* Link buffer 5
/* Link buffer control
/* Link common control
/* Link assignment register
/* Link service request and mask register */
/* Link path register 1
/* Link path register 2
/* Link path register 3
/* Link path counter
/* Link port constant 1 register
/* Link port constant 2 register
Control Register
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