Analog Devices ADSP-2106x SHARC User Manual page 650

E Control/Status Registers
LCTL
0x00C6
LEXT5
LBUF5 Extended Word Size
1=48-bit transfers
0=32-bit transfers
LEXT4
LBUF4 Extended Word Size
1=48-bit transfers
0=32-bit transfers
LEXT3
LBUF3 Extended Word Size
1=48-bit transfers
0=32-bit transfers
LEXT2
LBUF2 Extended Word Size
1=48-bit transfers
0=32-bit transfers
LEXT1
LBUF1 Extended Word Size
1=48-bit transfers
0=32-bit transfers
LEXT0
LBUF0 Extended Word Size
1=48-bit transfers
0=32-bit transfers
L3TRAN
LBUF3 Direction
1=Transmit, 0=Receive
L3CHEN
LBUF3 Chained DMA Enable
L3DEN
LBUF3 DMA Enable
L3EN
LBUF3 Enable
L2TRAN
LBUF2 Direction
1=Transmit, 0=Receive
L2CHEN
LBUF2 Chained DMA Enable
L2DEN
LBUF2 DMA Enable
L2EN
LBUF2 Enable
All control and status bits are active high unless otherwise
noted. Default bit values after reset are shown; if no value
E – 42 is shown, the bit is undefined at reset or depends upon
processor inputs. Reserved bits are shown with a gray
background. Reserved bits should always be written with zeros.
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
1=Enable, 0=Disable
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
L4EN
LBUF4 Enable
L4DEN
LBUF4 DMA Enable
L4CHEN
LBUF4 Chained DMA Enable
L4TRAN
LBUF4 Direction
1=Transmit, 0=Receive
L5EN
LBUF5 Enable
L5DEN
LBUF5 DMA Enable
L5CHEN
LBUF5 Chained DMA Enable
L5TRAN
LBUF5 Direction
1=Transmit, 0=Receive
L0EN
LBUF0 Enable
L0DEN
LBUF0 DMA Enable
L0CHEN
LBUF0 Chained DMA Enable
L0TRAN
LBUF0 Direction
1=Transmit, 0=Receive
L1EN
LBUF1 Enable
L1DEN
LBUF1 DMA Enable
L1CHEN
LBUF1 Chained DMA Enable
L1TRAN
LBUF1 Direction
1=Transmit, 0=Receive