Analog Devices ADSP-2106x SHARC User Manual page 639

Control/Status Registers
SYSTAT
31 30 29 28
0 0 0 0
0x0003
15 14 13 12
0 0 0 0
HPS
Host Packing Status
00 = packing complete
01 = first stage of all packing and unpacking modes
10 = second stage of 16-to-48 bit packing/unpacking or 32-to-48 bit packing/unpacking
All control and status bits are active high unless otherwise
noted. Default bit values after reset are shown; if no value
is shown, the bit is undefined at reset or depends upon
processor inputs. Reserved bits are shown with a gray
background. Reserved bits should always be written with zeros.
priority DMA requests occur. Maximum delay is 12 cycles.)
1=Direct write pending
0=No direct write pending
VIPD Vector Interrupt Pending—Indicates that a pending vector interrupt has
not yet been serviced. The VIPD bit is set when the VIRPT register is
written to and is cleared upon return from the interrupt service routine.
The host processor (or other ADSP-2106x) that issued the vector interrupt
should monitor this bit to determine when the service routine has been
completed (and when a new vector interrupt may be issued).
1=Vector interrupt pending
0=No vector interrupt pending
HPS(1:0) Host Packing Status—Indicates when host word packing is completed
or, if not, what stage of the process is taking place.
00=Packing complete
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27 26 25 24 23 22 21 20
0 0 0 0 0 0 0 0
11 10 9 8 7 6 5 4
0 0 0 0
E
19 18 17 16
0 0 0 0
3 2 1 0
0 0 0 0
HSTM
Host Mastership
BSYN
Bus Synchronization
CRBM
Current Bus Master
IDC
ID Code
DWPD
Direct Write Pending
VIPD
Vector Interrupt Pending
E – 31