Active Low Vs. Active High Frame Syncs - Analog Devices ADSP-2106x SHARC User Manual

10 Serial Ports
10.6.3

Active Low vs. Active High Frame Syncs

Frame sync signals may be either active high or active low (i.e.
inverted). The LTFS and LRFS bits of the STCTLx and SRCTLx control
registers determine the frame syncs' logic level.
When LTFS=0 or LRFS=0, the corresponding frame sync signal will be
active high.
When LTFS=1 or LRFS=1, the corresponding frame sync signal will be
active low.
Active high frame syncs are the default; the LTFS and LRFS bits are
initialized to 0 after a processor reset.
10.6.4 Sampling Edge For Data & Frame Syncs
Data and frame syncs can be sampled on either the rising or falling
edges of the serial port clock signals. The CKRE bit of the STCTLx and
SRCTLx control registers selects the sampling edge.
For transmit data and frame syncs, setting CKRE=1 in STCTLx selects
the rising edge of TCLKx. CKRE=0 selects the falling edge. Note that
data and frame sync signals will change state on the clock edge that is
not selected.
For receive data and frame syncs, setting CKRE=1 in SRCTLx selects
the rising edge of RCLKx. CKRE=0 selects the falling edge.
The transmit and receive functions of two serial ports connected
together, for example, should always select the same value for CKRE
so that any internally generated signals are driven on one edge and
any received signals are sampled on the opposite edge.
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