Early Vs. Late Frame Syncs - Analog Devices ADSP-2106x SHARC User Manual

10.6.5

Early vs. Late Frame Syncs

Frame sync signals can occur during the first bit of each data word
("late") or during the serial clock cycle immediately preceding the first
bit ("early"). The LAFS bit of the STCTLx and SRCTLx control registers
configures this option.
When LAFS=0, early frame syncs are configured; this is the normal
mode of operation. In this mode, the first bit of the transmit data word
is available (and the first bit of the receive data word is latched) in the
serial clock cycle after the frame sync is asserted, and the frame sync is
not checked again until the entire word has been transmitted (or
received). (In multichannel operation, this is the case when frame
delay is 1.)
If data transmission is continuous in early framing mode (i.e. the last
bit of each word is immediately followed by the first bit of the next
word), then the frame sync signal occurs during the last bit of each
word. Internally generated frame syncs are asserted for one clock cycle
in early framing mode.
When LAFS=1, late frame syncs are configured; this is the alternate
mode of operation. In this mode, the first bit of the transmit data word
is available (and the first bit of the receive data word is latched) in the
same serial clock cycle that the frame sync is asserted. (In multichannel
operation, this is the case when frame delay is zero.) Receive data bits
are latched by serial clock edges, but the frame sync signal is only
checked during the first bit of each word. Internally generated frame
syncs remain asserted for the entire length of the data word in late
framing mode. Externally generated frame syncs are only checked
during the first bit.
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