Systat Register Status Bits - Analog Devices ADSP-2106x SHARC User Manual

32-Bit to 48-Bit Word Packing (Host Bus
Data Bus Lines 47-32
1st transfer Word1, bits 47-32
2nd transfer Word2, bits 15-0
3rd transfer Word2, bits 47-32
The HMSWF bit of SYSCON is ignored for 32-to-48-bit packing.
The packing sequence for downloading or uploading ADSP-2106x
instructions over a 16-bit host bus takes 3 cycles for every word, as
shown below. The HMSWF bit in SYSCON determines whether the most
significant 16-bit word or least significant 16-bit word is packed first.
16-Bit to 48-Bit Word Packing w/HMSWF=1 (Host Bus
Data Bus Pins 31-16
1st transfer Word1 bits 47-32
2nd transfer Word1 bits 31-16
3rd transfer Word1 bits 15-0
40-bit extended precision data may be transferred using the 48-bit
packing mode. Refer to the Memory chapter of this manual for a
discussion of memory allocation for the different word widths.
8.6

SYSTAT REGISTER STATUS BITS

The SYSTAT register provides status information, primarily for
multiprocessor systems. Table 8.5 shows the status bits in this register.
Bit(s)
Name Definition
HSTM Host Mastership
BSYN Bus Synchronization
CRBM Current Bus Master (ID
IDC ID Code (ID
2-0
DWPD Direct Write Pending
VIPD Vector Interrupt Pending
HPS Host Packing Status
Table 8.5 SYSTAT Status Bits
www.BDTIC.com/ADI
Host Interface
ADSP-2106x):
Data Bus Lines 31-16
Word1, bits 31-16
Word1, bits 15-0
Word2, bits 31-16
of ADSP-2106x bus master)
2-0
of this ADSP-2106x)
8
ADSP-2106x):
8 – 29