Packing Status - Analog Devices ADSP-2106x SHARC User Manual

6 DMA
40-bit extended precision data may be transferred using the 48-bit
packing mode. Refer to the Memory chapter of this manual for a
description of memory allocation for different word widths.

6.4.1.2 Packing Status

Each external port DMA control register also contains a two-bit PS
field which contains the number of short words currently packed in
the EPBx buffer. During unpacking, the PS status behaves the same as
for packing. All of the packing functions are available for any type of
DMA transfer.
6.4.2 Internal & External Address Generation
DMA transfers between ADSP-2106x internal memory and external
memory require the DMA controller to generate addresses for both.
The external port DMA channels contain EI (External Index) and EM
(External Modifier) registers to perform external address generation.
The EI register provides the external port address for the current DMA
cycle, and is updated with the modifier value in EM for the next
external memory access.
In order to support the wide range of data packing operations
provided for external DMA transfers, the EI and EM registers are able
to generate addresses at a different rate than the internal address
registers (II and IM). For this reason the internal and external address
generators are decoupled from each other, and the EC (External Count)
register is used as the external DMA word counter.
If, for example, a 16-bit DMA device is reading data from ADSP-2106x
internal memory, then two external 16-bit transfers will occur for each
32-bit internal memory word and the EC (external) word count should
be twice the value of the C (internal) word count.
6.4.3 External Port DMA Modes
The MASTER, HSHAKE, and EXTERN bits of each DMACx control
register are used to select the DMA mode of operation. Each external
port DMA channel can be set up to operate in one of five DMA modes.
The master mode initiates transfers while the other modes act as
"slaves" where an external device must initiate each transfer.
The MASTER, HSHAKE, and EXTERN bits configure the DMA mode
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