Bit Instruction Packing - Analog Devices ADSP-2106x SHARC User Manual

8 Host Interface
• The host initiates another read access, driving the address of the data
to be accessed and then asserting
• The ADSP-2106x transmits the 2nd 16-bit word.
When a host writes a 32-bit word with 16-bit packing, again using the
typical bus interface hardware shown in Figure 8.8, the following
sequence of events occurs (also illustrated in Figure 8.5):
• The host initiates a write cycle by driving the write address, asserting
CS
if the access is asynchronous, and asserting
• The ADSP-2106x asserts REDY when it is ready to accept data.
• The host drives the address and the 1st 16-bit word, and deasserts
WR
(high).
• The ADSP-2106x latches the 1st 16-bit word.
• The host again drives the address and initiates another write cycle
for the 2nd 16-bit word, by asserting
• When the ADSP-2106x has accepted the 2nd word it performs an
internal direct write to its memory (or memory-mapped IOP
register). If the ADSP-2106x's internal write has not completed by
the time another host access occurs, that access will be held off with
REDY.
If the ADSP-2106x is waiting for another 16-bit word from the host to
complete the packed word, the HPS bits in the SYSTAT register will be
non-zero. (See "SYSTAT Register Status Bits.") Because there is only
one packing buffer for the host interface, the host must fully complete
each packed read or write before another is begun.
8.5.4

48-Bit Instruction Packing

The host can also download and upload 48-bit instructions over its
16- or 32-bit bus. The packing sequence for downloading ADSP-2106x
instructions from a 32-bit host bus (HPM=11) takes 3 cycles for every
2 words, as illustrated below. 32-bit data is transferred on data bus
lines 47-16 (DATA
transferred, the packing buffer must be flushed by a dummy access to
remove the unused word.
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RD
.
WR
). If an odd number of instruction words are
47-16
WR
(low).
.