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ADSP-2181/ADSP-2183
When the IDLE (n) instruction is used, it effectively slows down
the processor's internal clock and thus its response time to in-
coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2181/ADSP-2183 will remain
in the idle state for up to a maximum of n processor cycles (n =
16, 32, 64, or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor's reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows a typical basic system configuration with the
ADSP-2181/ADSP-2183, two serial devices, a byte-wide
EPROM, and optional external program and data overlay
memories. Program-mable wait state generation allows the pro-
cessor connects easily to slow peripheral devices. The ADSP-
2181/ADSP-2183 also provides four external interrupts and two
serial ports or six external interrupts and one serial port.
ADSP-2181/
ADSP-2183
1/2x CLOCK
CLKIN
OR
ADDR13-0
CRYSTAL
XTAL
FL0-2
PF0-7
DATA23-0
IRQ2
IRQE
IRQL0
IRQL1
SPORT1
SCLK1
RFS1 OR IRQ0
SERIAL
DEVICE
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT0
SCLK0
RFS0
SERIAL
TFS0
DEVICE
DT0
DR0
IDMA PORT
IRD
SYSTEM
IWR
INTERFACE
IS
OR
IAL
µCONTROLLER
IACK
PWDACK
16
IAD15-0
Figure 2. ADSP-2181/ADSP-2183 Basic System Configuration
Clock Signals
The ADSP-2181/ADSP-2183 can be clocked by either a crystal
or by a TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User's Manual for detailed information on
this power-down feature.
If an external clock is used, it should be a TTL-compatible sig-
nal running at half the instruction rate. The signal is connected
to the processor's CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.
A
14
13-0
D
A0-A21
23-16
BYTE
D
24
15-8
MEMORY
DATA
CS
BMS
A
10-0
ADDR
D
23-8
I/O SPACE
DATA
(PERIPHERALS)
2048 LOCATIONS
CS
IOMS
A
13-0
ADDR
OVERLAY
D
23-0
MEMORY
DATA
TWO 8K
PMS
PM SEGMENTS
DMS
TWO 8K
CMS
DM SEGMENTS
BR
BG
BGH
PWD
The ADSP-2181/ADSP-2183 uses an input clock with a fre-
quency equal to half the instruction rate; a 16.67 MHz input
clock yields a 30 ns processor cycle (which is equivalent to
33 MHz). Normally, instructions are executed in a single pro-
cessor cycle. All device timing is relative to the internal instruc-
tion clock rate, which is indicated by the CLKOUT signal when
enabled.
Because the ADSP-2181/ADSP-2183 includes an on-chip oscil-
lator circuit, an external crystal may be used. The crystal should
be connected across the CLKIN and XTAL pins, with two capaci-
tors connected as shown in Figure 3. Capacitor values are de-
pendent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency, mi-
croprocessor-grade crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor's cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control
Register.
CLKIN
ADSP-2181/
ADSP-2183
Figure 3. External Crystal Connections
Reset
The RESET signal initiates a master reset of the ADSP-2181/
ADSP-2183. The RESET signal must be asserted during the
power-up sequence to assure proper initialization. RESET dur-
ing initial power-up must be held long enough to allow the in-
ternal clock to stabilize. If RESET is activated any time after
power up, the clock continues to run and does not require
stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
mum pulse width specification, t
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an ex-
ternal Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000 once
boot loading completes.
–6–
XTAL
CLKOUT
is ap-
DD
.
RSP
REV. 0
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