Data Transfers Through The Epbx Buffers - Analog Devices ADSP-2106x SHARC User Manual

7 Multiprocessing
If 48-bit accesses and 32-bit accesses to the same locations absolutely
must be mixed in this way, you must flush out the shadow FIFO with
two dummy writes before attempting to read the data.
7.5

DATA TRANSFERS THROUGH THE EPBx BUFFERS

In addition to direct reads and writes, the ADSP-2106x bus master can
transfer data to and from the slave ADSP-2106xs through the external
port FIFO buffers, EPB0, EPB1, EPB2, and EPB3. Each of these buffers,
which are part of the IOP register set, is a six-location FIFO. Both
single-word transfers and DMA transfers can be performed through
the EPBx buffers. DMA transfers are handled internally by the
ADSP-2106x's DMA controller, but single-word transfers must be
handled by the ADSP-2106x core.
Each EPBx buffer has a read port and a write port, both of which can
connect internally to either the EPD (External Port Data) bus or to a
local bus which in turn can connect to the IOD (I/O Data) bus, PM
Data bus, or DM Data bus. This is shown in Figure 8.1 in the
Host Interface chapter. Note that direct reads and writes bypass the
EPBx buffers and go directly to internal memory.
7.5.1 Single-Word Transfers
When the ADSP-2106x master writes a single data word to a slave's
EPBx buffers, the slave core's program must read the data. Conversely,
when the slave's core writes a single piece of data to one of its EPBx
buffers, the master must perform an external bus read cycle to obtain
it. Because the EPBx buffers are six-deep FIFOs (in both directions), the
master and the slave's core are allowed extra time to read the data—
efficient, continuous, single-word transfers can thus be performed in
real-time, with low latency and without using DMA.
If the ADSP-2106x master attempts a read from an empty EPBx buffer
on a slave, the access will be held off with the ACK signal until the
buffer receives data from the slave's core. If the slave's core attempts to
write to a full EPBx buffer, the access is also delayed and the core will
hang until the buffer is externally read by the master. To prevent this
from happening, the BHD (Buffer Hang Disable) bit should be set to 1
in the SYSCON register. The full or empty status of a particular EPBx
buffer can be determined by reading the appropriate DMACx control/
status register.
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