Data-Independent Transmit Frame Sync - Analog Devices ADSP-2106x SHARC User Manual

10 Serial Ports
Figure 10.7 illustrates the two modes of frame signal timing:
• LAFS bits of STCTLx, SRCTLx control registers. LAFS=0 for early
frame syncs, LAFS=1 for late frame syncs.
• Early framing: frame sync precedes data by one cycle. Late framing:
frame sync checked on first bit only.
• Data transmitted MSB-first (SENDN=0) or LSB-first (SENDN=1).
• Frame sync and clock generated internally or externally.
xCLK
Late
Frame
Sync
Early
Frame
Sync
Data
Figure 10.7 Normal vs. Alternate Framing
10.6.6

Data-Independent Transmit Frame Sync

Normally the internally generated transmit frame sync signal (TFS) is
output only when the TX buffer has data ready to transmit. The DITFS
mode (data-independent transmit frame sync) allows the continuous
generation of the TFS signal, with or without new data. The DITFS bit
of the STCTLx control register configures this option.
When DITFS=0, the internally generated TFS is only output when a
new data word has been loaded into the TX buffer. Once data is loaded
into TX, it is not transmitted until the next TFS is generated. This mode
of operation allows data to be transmitted only at specific times.
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