Figure 7.5 Bus Arbitration Timing - Analog Devices ADSP-2106x SHARC User Manual

7 Multiprocessing
The following steps summarize the actions a slave takes to acquire bus
mastership and perform an external read or write over the bus (see
Figure 7.6):
1. The slave determines that it is executing an instruction which
requires an off-chip access. It asserts its
the cycle. Extra cycles are generated by the core processor (or DMA
controller) until the slave acquires bus mastership.
2. To acquire bus mastership, the slave waits for a bus transition cycle
in which the current bus master deasserts its
has the highest priority request in the bus transition cycle, it
becomes the bus master in the next cycle. If not, it continues
waiting.
SYSTEM CLOCK
Bus Requests:
BR1
BR2
ADSP-2106x #1
is the Bus Master
ADSP-2106x w/ ID=1:
Internal
EXECUTION FLOW
Operation
Hold control signals stable
BUS ACTIVITY
ADSP-2106x w/ ID=2:
Internal
EXECUTION FLOW
Operation
BUS ACTIVITY

Figure 7.5 Bus Arbitration Timing

7 – 12
www.BDTIC.com/ADI
BRx sampled at this point
Bus Transition
Cycle
Internal
Internal
Operation
Operation
External Access
Perform
Undriven
Access
BR
x line at the beginning of
BR
x line. If the slave
ADSP-2106x #2
is the Bus Master
Internal Internal
Operation Operation
Undriven
Extermal Internal Extermal
Access Operation Access
Perform Hold signals Perform
Access stable Access
Bus Transition ADSP-2106x #1
Cycle is the Bus Master
External Access
Perform
Access
Internal Internal
Operation Operation
Hold signals
Undriven
stable