Core Priority Access - Analog Devices ADSP-2106x SHARC User Manual

7 Multiprocessing
7.3.4

Core Priority Access

CPA
The Core Priority Access signal, , allows external bus accesses by
the core processor of a slave ADSP-2106x to take priority over ongoing
DMA transfers. Normally when external port DMA transfers are in
progress, the core processors of the slave ADSP-2106xs cannot use the
CPA
external bus until the DMA transfer is finished. By asserting its
pin, the core processor of a slave ADSP-2106x can acquire the bus
without waiting for the DMA operation to complete.
CPA
If the signal is not used in a multiprocessor system, the
ADSP-2106x bus master will not give up the bus to another
ADSP-2106x until either: 1) a cycle in which it does not perform an
external bus access, or 2) a bus timeout. If a slave ADSP-2106x needs to
send a high priority message or perform an important data transfer, it
normally must wait until any DMA operation completes. Using the
CPA
signal allows the slave to perform its higher priority bus access
with less delay.
A slave ADSP-2106x core with a pending access to the bus will assert
CPA BR CPA
the pin at the same time as its bus request pin ( x). is an
open-drain output which is connected to all ADSP-2106xs in the
system. Each ADSP-2106x has a 5 Kohm pull-up resistor on this pin,
allowing it to be shared among all ADSP-2106xs in the system. Any
CPA
ADSP-2106x may assert low, and the internal resistors (or an
additional external resistor for faster pull-up) will pull it high when it
is released. Multiple ADSP-2106xs can be asserting this line at the same
time.
CPA
When is asserted, the current ADSP-2106x bus master will
BR
deassert its x and give up the bus, provided its core does not have
an external access pending. In addition, any ADSP-2106x cores that do
BR
not have an external access pending will remove their x pins in the
CPA
next cycle. Note that the current bus master never asserts because
it already has control of the bus.
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