One- & Two-Instruction Loops - Analog Devices ADSP-2106x SHARC User Manual

11 System Design
11.7.1.4 One- & Two-Instruction Loops
Counter-based loops that have only one or two instructions can cause
delays if not executed a minimum number of times. The ADSP-2106x
checks the termination condition two cycles before it exits the loop. In
these short loops, the ADSP-2106x has already looped back when the
termination condition is tested. Thus, if the termination condition tests
true, the two instructions in the pipeline must be aborted and NOPs
executed instead.
Specifically, a loop of length one executed one or two times or a loop of
length two executed only once incurs two cycles of overhead because
there are two aborted instructions after the last iteration. Note that
these overhead cycles are in addition to any extra cycles caused by a
PM bus data access inside the loop (see previous section). To avoid
overhead, use straight-line code instead of loops in these cases.
11.7.1.5 DAG Register Writes
When an instruction that writes to a DAG register is followed by an
instruction that uses any register in the same DAG for data addressing,
modify instructions, or indirect jumps, the ADSP-2106x inserts an extra
(NOP) cycle between the two instructions. This happens because the
same bus is needed by both operations in the same cycle, therefore the
second operation must be delayed. An example is:
L2=8;
DM(I0,M1)=R1;
Because L2 is in the same DAG as I0 (and M1), an extra cycle is
inserted after the write to L2.
11.7.1.6 Wait States
An external memory access can be programmed to include a specific
number of wait states and bus idle cycles, and (or) to wait for an
external acknowledge signal (ACK) before completing. If only
internally programmed wait states and bus idle cycles are used, the
delay is exactly the number of wait states and bus idle cycles
(1 waitstate = 1 cycle). If the external acknowledge signal is used,
either alone or in combination with programmed wait states, the delay
depends on the external system and can vary.
11.7.2 Delayed Branch Restrictions
A delayed branch instruction and the two instructions that follow it
must be executed sequentially. Any interrupt that occurs between a
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