Analog Devices ADSP-2106x SHARC User Manual page 443

Memory Stalls
• 1 cycle on PM and DM bus accesses to the same block of internal
memory
• n cycles if conflicting accesses to external memory (PM and DM bus
accesses must complete)
• n cycles if access to external memory (until I/O buffers are cleared out)
• n cycles if external access and ADSP-2106x does not own external bus
• n cycles until external access is complete (i.e. waitstates, idle cycles, etc.)
IOP Register Stalls
• n cycles if PM and DM bus access to IOP registers (both must complete)
• n cycles if conflict with slave access
DMA Stalls
• 1 cycle if an access to a DMA parameter register conflicts with the DMA
address generation (i.e. writing to the register while a register update is
taking place or reading while a DMA register read is taking place)
• 1 cycle if an access to a DMA parameter register conflicts with DMA
chaining
• n cycles if writing (reading) to a DMA buffer and the buffer is full
(empty)
Link Port & Serial Port Stalls
• 1 cycle if two link buffer reads back-to-back
• n cycles if write to a full buffer or read from an empty buffer
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System Design 11
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