Analog Devices ADSP-2106x SHARC User Manual page 173

5.4.5.1 Suspend Bus Tristate (
External devices can assert the ADSP-2106x's
external bus address, data, selects, and strobes in a high-impedance
state for the following cycle. If the ADSP-2106x attempts to access
SBTS
external memory while
the memory access will not be completed until
SBTS
should only be used to recover from DRAM page faults or host
processor/ADSP-2106x deadlock. (See "Deadlock Resolution" in the
"System Bus Interfacing" section of the Host Interface chapter.) In the
case of DRAM page faults,
to take control of the external bus.
SBTS
causes the following pins to be tristated:
RD
ADDR
31-0
WR
DATA
47-0
MS SW
BMS 3-0
ADRCLK
SBTS SBTS
5.4.5.2 Normal Operation:
SBTS
Asserting places the external bus address, data, selects, and
strobes in a high-impedance state for the following cycle. If an external
SBTS
access is underway when
(as if ACK were deasserted). If
external access occurring, the external bus pins will tristate and the
ADSP-2106x will continue running until it tries to perform an external
access (at which time it will halt). In this case, the memory access will
begin in the cycle after the deassertion of
SBTS
When is deasserted, the
reasserted (if they had been asserted prior to
address has become valid (i.e. at their normal timing within the cycle).
The wait state counter will be reset. This applies even if the processor
RESET
is held in reset ( asserted).
SBTS HBR
differs from in that it takes effect in the next cycle, even if an
external access is occurring (but not finished).
used when the external access is to a device such as a DRAM or cache
memory, where the access must be held off in order to prepare for it.
SBTS
Use of at other times—such as during ADSP-2106x-to-
ADSP-2106x accesses or when
incorrect operation.
www.BDTIC.com/ADI
SBTS
SBTS
)
SBTS
input to place the
is asserted, the processor will halt and
SBTS
is deasserted.
SBTS
allows the external DRAM controller
PAGE
DMAG1
DMAG2
HBR HBR
Not Asserted
is asserted, the access will be held off
SBTS
is asserted while there is no
SBTS
.
RD WR DMAG
, , and x strobes will be
SBTS
) after the external
SBTS
should only be
DMAG
x is asserted—will result in
Memory 5
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