Link Port Booting - Analog Devices ADSP-2106x SHARC User Manual

11 System Design
return execution to the reset routine at location 0x0002 0005 where
normal program execution can resume. After this 256 word load and
RTI have occurred, your program can write a different service routine
at the EP0I vector location 0x0002 0040. These 256 instructions must
serve as a loader that loads the rest of your program.
Note that External Port DMA Channel 6 must be used for the initial
instruction download because only this channel has its IMASK bit set
to enable a DMA done interrupt. VIRPT vector interrupts are disabled
at reset, and must be enabled by your ADSP-2106x program (in the
IMASK register).
Note that a master ADSP-2106x may boot a slave ADSP-2106x by
writing to its DMAC6 control register and setting the packing mode
(PMODE) to 00. This allows instructions to be downloaded directly
without packing. The wait state setting of 6 on the slave ADSP-2106x
does not affect the speed of the download since wait states only affect
bus master operation.
11.6.4

Link Port Booting

The ADSP-2106x can also be booted through Link Buffer 4 using DMA
Channel 6. A four-bit-wide external device must be used to download
instructions after system powerup. The output of an eight-bit-wide
EPROM can be converted to nibble data by using a 2-to-1 multiplexer
on the output, with the address LSB selecting the high- or low-order
nibble.
The external device must provide a clock signal to the link port
assigned to link buffer 4. The clock can be any frequency, up to a
maximum of the ADSP-2106x clock frequency. The clock's falling
edges strobe the data into the link port. The most significant 4-bit
nibble of the 48-bit instruction must be downloaded first.
The link port booting operation is similar to the host booting
operation; the II6 and C6 parameter registers for DMA Channel 6 are
initialized to the same values. The DMA Channel 6 Control Register
(DMAC6) is initialized to 0x00A0, which disables external port DMA
and selects DTYPE for instruction words. The LCTL and LCOM link
port control registers are overridden during link port booting to allow
link buffer 4 to receive 48-bit data. Form more information on the
booting process, see the Host Booting section.
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