Dag Register Transfers; Dag Register Transfers - Analog Devices ADSP-2106x SHARC User Manual

4.4

DAG REGISTER TRANSFERS

DAG registers are part of the universal register set and may be written to
from memory, from another universal register, or from an immediate field
in an instruction. DAG register contents may be written to memory or to a
universal register.
Transfers between 32-bit DAG1 registers and the 40-bit DM Data Bus are
aligned to bits 39-8 of the bus. When 24-bit DAG2 registers are read to the
40-bit DM Data Bus, M register values are sign-extended to 32 bits and I,
L, and B register values are zero-filled to 32 bits. The results are aligned to
bits 39-8 of the DM Data Bus. When DAG2 registers are written from the
DM Data Bus, bits 31-8 are transferred and the rest are ignored. Figure 4.5
illustrates these transfers.
39
DAG1 Register (7-0)
39 23
8 SIGN BITS DAG2 M Register (15-8)
Figure 4.5 DAG Register Transfers
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Data Addressing
7 0 39
8 ZEROS 8 ZEROS
7 0 39
8 ZEROS
23 7
8 ZEROS
DAG2 I, L, or B Register (15-8)
23 7
DAG2 M Register (15-8)
4 – 11
4
0
0