Analog Devices ADSP-2106x SHARC User Manual page 11

9.5.1 DMA Chaining For Link Ports ........................................................................9-18
9.6 LINK PORT INTERRUPTS ................................................................................9-18
9.6.1 Link Port Interrupts With DMA Disabled ........................................................9-18
9.6.2 Link Port Interrupts With DMA Enabled .........................................................9-19
9.6.3 Link Port Service Request Interrupts (LSRQ) ................................................9-19
9.7 TRANSMISSION ERROR DETECTION ............................................................9-23
9.8 TOKEN PASSING ..............................................................................................9-23
9.9 LINK TRANSMISSION LINES ............................................................................9-26
9.10 SYSTEM DESIGN EXAMPLE: LOCAL DRAM INTERFACE .............................9-27
9.11 PROGRAMMING EXAMPLES ...........................................................................9-28
9.11.1 Core-Driven Single-Word Transfers ...............................................................9-28
9.11.2 DMA Transfers ...............................................................................................9-28
CHAPTER 10 SERIAL PORTS
10.1 OVERVIEW ........................................................................................................10-1
10.1.1 SPORT Interrupts ..........................................................................................10-4
10.2 SPORT RESET ..................................................................................................10-4
10.3 SPORT CONTROL REGISTERS & DATA BUFFERS .......................................10-5
10.3.1 Register Writes & Effect Latency ...................................................................10-6
10.3.2 Transmit & Receive Data Buffers (TX, RX)....................................................10-7
10.3.2.1 Reading & Writing RX, TX .........................................................................10-8
10.3.3 Transmit & Receive Control Registers (STCTL, SRCTL) ..............................10-8
10.3.4 Clock & Frame Sync Frequencies (TDIV, RDIV) .........................................10-13
10.3.4.1 Maximum Clock Rate Restrictions ...........................................................10-15
10.4 DATA WORD FORMATS .................................................................................10-16
10.4.1 Word Length ................................................................................................10-16
10.4.2 Endian Format .............................................................................................10-16
10.4.3 Data Packing & Unpacking ..........................................................................10-16
10.4.4 Data Type ....................................................................................................10-17
10.4.5 Companding .................................................................................................10-18
10.5 CLOCK SIGNAL OPTIONS ..............................................................................10-19
10.5.1 Internal vs. External Clocks .........................................................................10-19
10.6 FRAME SYNC OPTIONS .................................................................................10-20
10.6.1 Framed vs. Unframed ..................................................................................10-20
10.6.2 Internal vs. External Frame Syncs ...............................................................10-21
10.6.3 Active Low vs. Active High Frame Syncs.....................................................10-22
10.6.4 Sampling Edge For Data & Frame Syncs ....................................................10-22
10.6.5 Early vs. Late Frame Syncs .........................................................................10-23
10.6.6 Data-Independent Transmit Frame Sync .....................................................10-24
10.7 MULTICHANNEL OPERATION .......................................................................10-25
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