Figure 10.2 Stctl0, Stctl1 Transmit Control Registers - Analog Devices ADSP-2106x SHARC User Manual

10 Serial Ports
TXS
TX Data Buffer Status (read-only)
11=full, 00=empty, 10=partially full
TUVF
Transmit Underflow Status (sticky, read-only)
CHNL
Current Channel Select (read-only)
MFD
Multichannel Frame Delay
DITFS
Data-Independent TFS
1=data-independent, 0=data-dependent
ITFS*
Internally Generated TFS
1=internal TDFS, 0=external TFS
TFSR*
Tranmsit Frame Sync Required
1=TFS required, 0=TFS not required
CKRE
Clock Edge for Data, Frame Sync Sampling
1=rising edge, 0=falling edge

Figure 10.2 STCTL0, STCTL1 Transmit Control Registers

10 – 10
www.BDTIC.com/ADI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6
0 0 0 0 0 0 0 0 0 0
* Must be cleared for multichannel operation.
16
0 0 0 0 0 0
LTFS
Active Low TFS
1=active low, 0=active high
LAFS*
Late TFS
1=late TFS, 0=early TFS
SDEN
SPORT Transmit DMA Enable
1=enable DMA, 0=disable DMA
SCHEN
SPORT Transmit DMA Chaining Enable
1=enable chaining, 0=disable chaining
5 4 3 2 1 0
0 0 0 0 0 0
SPEN*
SPORT Enable
1=enable, 0=disable
DTYPE
Data Type
SENDN
Serial Word Endian
0=MSB-first, 1=LSB-first
SLEN
Serial Word Length – 1
PACK
16-bit to 32-bit Word Packing
1=packing, 0=no packing
ICLK
Internally Generated Receive Clock
1=internal clock, 0=external clock