Analog Devices ADSP-2106x SHARC User Manual page 688

Index
BMS ............... 5-39, 5-42, 11-31, 11-35, E-24
Board-level testing ................................. 11-15
Boot EPROM ............................................. E-24
Booting ..................... 3-26, 3-28, 11-27, E-34
Booting mode .............................................. F-2
Bootstrapping ............................. 11-29, 11-31
Boundary scan ............................... 11-13, D-1
BR0 bit ........................................................ 4-10
BR8 bit ........................................................ 4-10
Branch ........................................ 3-6, 3-9, 3-24
Broadcast write ............ 5-18, 7-7, 7-30, 7-31
Broadcast write timing ............................ 7-24
BRx ............................................... 7-9, 8-3, 8-6
BSDL file ..................................................... D-2
BSO bit (SYSCON register) ................... 11-31
BSYN bit (SYSTAT register) .................... 7-20
Buffer base address .................................... 4-1
Buffer hang disable (BHD) .......... 6-42, 8-18,
................... 9-16, 10-8, 10-36, E-24, E-28
Buffer status .............. 7-27, 9-14, 9-16, 9-19,
....... 10-7, 10-36, E-28, E-37, E-45, E-49
Bus arbitration timing .............................. 7-12
Bus exchange .............................................. A-6
Bus idle cycle ....................... 5-40, 5-41, 5-43,
.................................................. 11-40, E-33
Bus lock ........................................... 8-38, E-16
Bus master ............................. 7-16, 7-18, 7-19
Bus master condition (BM) .... 3-7, 3-8, E-14
Bus mastership .......................................... 7-11
Bus request prioritization ............. 6-26, 7-11
Bus slave .................................................... 3-24
Bus synchronization ................................ E-30
Bus timeout ............................................... 7-16
Bus transition cycle ...... 7-11, 7-18, 8-6, 8-7,
..................................................... 8-11, G-2
BUSLK bit (MODE2 register) .................. 7-30
Bypass capacitors ................................... 11-25
C
C Compiler ............................................... A-54
CACC ........................................................... 2-9
Cache disable .................................. 3-41, E-16
Cache flush ............................................... A-50
Cache freeze .................................... 3-41, E-16
Cache miss ................. 3-38, 3-39, 3-40, 3-41,
................................................. 11-39, 11-44
Cache-inefficient code .............................. 3-40
CADIS (cache enable/disable) ............... 3-41
CAFRZ (cache freeze) .............................. 3-41
X – 2
www.BDTIC.com/ADI
CALL instruction ..................... 3-6, 3-9, 3-15
Capacitive loading ................................. 11-22
Carry flag ..................................................... 2-9
CB15I interrupt ......................................... 3-25
CB7I interrupt ........................................... 3-25
CCITT G.711 specification ..................... 10-18
Chain insertion mode ................... 6-10, 6-32,
..................................................... 6-34, 6-35
Chain pointer .................................. 6-23, 6-30
Chain pointer register (CP) 6-22, 6-24, 6-28,
.......................................... 6-29, 6-32, 6-35
Chained DMA ..................... 6-10, 6-22, 6-28,
.................................................... 6-29, E-39
Chained DMA sequences ........................ 6-31
Circuit board layout ............................... 11-18
Circular buffer addressing ........................ 4-6
Circular buffer base address ............. 4-1, 4-6
Circular buffer interrupts ............... 3-25, 4-8
Circular buffer overflow ...... 3-21, 3-25, 4-8,
...................................................... 4-9, E-22
Circular buffer placement ......................... 1-6
Circular buffers ... 1-9, 4-1, 4-6, 11-41, E-20
Clear interrupt (CI) ............... 3-26, 3-30, A-5
Clipping ....................................................... 2-9
CLKIN ............................. 11-10, 11-17, 11-18
Clock distribution ...................... 11-16, 11-26
Clock frequencies ................................... 11-18
Clock jitter ............................................... 11-19
Clock oscillators ...................................... 11-26
Clock skew .................................. 11-16, 11-19
Clock tree ................................................. 11-16
Cluster multiprocessing ............................ 7-4
CMOS input ............................................ 11-17
Coefficients .................................................. 5-4
Companding ................... 10-17, 10-25, 10-29
Compare accumulation (CACC) ...... 2-7, 2-9
Compare flags ............................................. 2-9
Compare operations .......................... 2-7, 2-9
Complex data ............................................ 1-17
Complex math .......................................... 2-13
Compute field ............................................. B-1
Compute operations .................................. B-1
Condition codes ................................ 3-8, A-5
Condition complements ............................ 3-7
Conditional instructions ................ 3-7, 7-10,
....................................................... A-1, E-3
Conditional memory read instruction .. 5-49
Conditional memory write
instruction .................... 5-37, 5-38, 5-50