Analog Devices ADSP-2106x SHARC User Manual page 625

Control/Status Registers
31
MODE2
Processor ID
Silicon Revision #
15 14
0
0=FLAG0 Input
FLG0O
1=FLAG0 Output
0=No External Bus Lock
BUSLK
1=External Bus Lock
0=Disable Timer
TIMEN
1=Enable Timer
0=Enable Cache
CADIS
1=Disable Cache
All control and status bits are active high unless otherwise
noted. Default bit values after reset are shown; if no value
is shown, the bit is undefined at reset or depends upon
processor inputs. Reserved bits are shown with a gray
background. Reserved bits should always be written with zeros.
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30 29 28 27 26 25 24 23 22
0 0 0 0 0 0
13 12 11 10 9 8 7 6
0 0 0 0 0 0 0 0 0
21 20 19 18 17 16
0 0 0 0 0 0
FLG1O 0=FLAG1 Input
1=FLAG1 Output
FLG2O 0=FLAG2 Input
1=FLAG2 Output
FLG3O 0=FLAG3 Input
1=FLAG3 Output
CAFRZ 0=Cache Updates
1=Cache Freeze (No Updates)
5 4 3 2 1 0
0 0 0 0 0 0
IRQ0E 0=IRQ0 Level-Sensitive
1=IRQ0 Edge-Sensitive
0=IRQ1 Level-Sensitive
IRQ1E
1=IRQ1 Edge-Sensitive
IRQ2E 0=IRQ2 Level-Sensitive
1=IRQ2 Edge-Sensitive
E
E – 17