E.20 Sport Divisors (Tdiv, Rdiv) - Analog Devices ADSP-2106x SHARC User Manual

0x00E1
0x00F1
TDIV0
TDIV1
31 30 29
15 14 13
Control/Status Registers
E.20 SPORT DIVISORS (TDIV, RDIV)
The TDIV0, TDIV1, RDIV0, and RDIV1 registers contain divisor values
that determine the frequencies for internally generated serial port
clocks and frame syncs. These four registers are memory-mapped at
addresses 0x00E4, 0x00F4, 0x00E6, and 0x00F6 respectively. These
registers are not initialized after reset.
TDIVx
Bits Name Definition
15-0 TCLKDIV Transmit Clock Divisor
31-16 TFSDIV Transmit Frame Sync Divisor
RDIVx
Bits Name Definition
15-0 RCLKDIV Receive Clock Divisor
31-16 RFSDIV Receive Frame Sync Divisor
28 27 26 25 24 23 22 21 20
TFSDIV
Transmit Frame Sync Divisor
12 11 10 9 8 7 6 5 4
TCLKDIV
Transmit Clock Divisor
xCLKDIV =
xFSDIV =
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RDIV0
0x00E4
RDIV1
0x00F4
19 18 17 16 31 30 29 28
15 14 13 12
3 2 1 0
f
CLKIN
– 1
serial clock frequency
serial clock frequency
– 1
frame sync frequency
E
27 26 25 24 23 22 21 20 19
RFSDIV
Receive Frame Sync Divisor
11 10 9 8 7 6 5 4 3
RCLKDIV
Receive Clock Divisor
E – 53
0x00E6
0x00F6
18 17 16
2 1 0