Delayed & Nondelayed Branches; Nondelayed Branches - Analog Devices ADSP-2106x SHARC User Manual

3 Program Sequencing
3.4.1 Delayed & Nondelayed Branches
An instruction modifier (DB) indicates that a branch is delayed; otherwise,
it is nondelayed. If the branch is nondelayed, the two instructions after the
branch, which are in the fetch and decode stages, are not executed (see
Figure 3.4); for a call, the decode address (the address of the instruction
after the call) is the return address. During the two no-operation cycles,
the first instruction at the branch address is fetched and decoded.
NON-DELAYED JUMP OR CALL
CLOCK CYCLES
Execute
n
Instruction
Decode
n+1->nop
Instruction
Fetch
n+2
Instruction
n+1 suppressed
NON-DELAYED RETURN
CLOCK CYCLES
Execute
n
Instruction
Decode
n+1->nop
Instruction
Fetch
n+2
Instruction
n+1 suppressed
n = Branch instruction
j = Instruction at Jump or Call address
r = Instruction at Return address
Figure 3.4 Nondelayed Branches
3 – 10
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nop
n+2->nop
j
n+2 suppressed; for
call, n+1 pushed on
PC stack
nop
n+2->nop
r
n+2 suppressed; r
popped from PC
stack
nop j
j j+1
j+1 j+2
nop r
r r+1
r+1 r+2