Analog Devices ADSP-2106x SHARC User Manual page 7

5.2 ADSP-2106X MEMORY MAP ..............................................................................5-9
5.2.1 ADSP-21060 Internal Memory Space ............................................................5-11
5.2.2 ADSP-21062 Internal Memory Space ............................................................5-14
5.2.3 ADSP-21061 Internal Memory Space ............................................................5-16
5.2.4 Porting Code from ADSP-21060 to ADSP-21062 or ADSP-21061 ................5-18
5.2.5 Multiprocessor Memory Space ......................................................................5-18
5.2.6 External Memory Space .................................................................................5-19
5.2.7 Memory Space Access Restrictions ..............................................................5-19
5.3 INTERNAL MEMORY ORGANIZATION & WORD SIZE ...................................5-20
5.3.1 32-Bit Words & 48-Bit Words .........................................................................5-20
5.3.2 Mixing 32-Bit & 48-Bit Words In One Memory Block .....................................5-23
5.3.3 Basic Examples Of Mixed 32-Bit & 48-Bit Words ..........................................5-24
5.3.4 16-Bit Short Words .........................................................................................5-27
5.3.5 Mixing 32-Bit & 48-Bit Words With Finer Granularity .....................................5-28
5.3.5.1 Low-Level Physical Mapping Of Memory Blocks .......................................5-29
5.3.5.2 Placement Restrictions For Mixed 32-Bit & 48-Bit Words .........................5-30
5.3.5.3 Shadow Write FIFO ...................................................................................5-33
5.3.6 Configuring Memory For 32-Bit or 40-Bit Data ...............................................5-34
5.4 EXTERNAL MEMORY INTERFACING ..............................................................5-35
5.4.1 External Memory Banks .................................................................................5-38
5.4.2 Unbanked Memory .........................................................................................5-38
5.4.3 Boot Memory Select (BMS) ...........................................................................5-39
5.4.4 Wait States & Acknowledge ...........................................................................5-39
5.4.4.1 WAIT Register ...........................................................................................5-40
5.4.4.2 Multiprocessor Memory Space Wait States & Acknowledge .....................5-44
5.4.5 DRAM Page Boundary Detection ..................................................................5-44
5.4.5.1 Suspend Bus Tristate (SBTS) ...................................................................5-47
5.4.5.2 Normal SBTS Operation: HBR Not Asserted ............................................5-47
5.5 EXTERNAL MEMORY ACCESS TIMING ..........................................................5-48
5.5.1 External Memory ............................................................................................5-48
5.5.1.1 External Memory Read - Bus Master ........................................................5-48
5.5.1.2 External Memory Write - Bus Master ........................................................5-49
5.5.2 Multiprocessor Memory ..................................................................................5-50
CHAPTER 6 DMA
6.1 OVERVIEW ..........................................................................................................6-1
6.1.1 DMA Controller Features .................................................................................6-5
6.1.2 Setting Up DMA Transfers ...............................................................................6-6
6.2 DMA CONTROL REGISTERS .............................................................................6-7
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Contents
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