Link Transmission Lines - Analog Devices ADSP-2106x SHARC User Manual

9 Link Ports
• Ensure that the link interrupt selection matches the application. If a
status detection scheme using the status bits of the LSRQ register is to
be used, it is important to note the following: If a link port that is
configured to receive is disabled while LxACK is asserted, there will be
an RC delay before the 50k ohm pulldown resistor on LxACK (if
enabled) can pull the value below logic threshold. Likewise, if a link
port that is configured to transmit is disabled while LxCLK is asserted,
there will be an RC delay before the 50k ohm pulldown resistor on
LxCLK (if enabled) can pull the value below logic threshold. If the
appropriate request status bit is unmasked in the LSRQ register (in this
instance), then an LSR will be latched and the LSRQ interrupt may be
serviced, even though unintended, if enabled.
• Ensure that synchronization is not disrupted by unrelated influences at
critical sections where timing control loops are used to synchronize
parallel code execution. Disabling of nested interrupts is one of the
techniques used in the example to control this.
9.9

LINK TRANSMISSION LINES

The link ports are designed to allow long distance connections to be
made between the driver and the receiver. This is possible because the
links are self-synchronizing, i.e. the clock and data are transmitted
together. Only relative delay, not absolute delay between clock and
data is of importance.
In addition, the LACK signal inhibits transmission of the next word,
not of the current nibble (i.e. the current word is always allowed to
complete transmission). This allows delays of 2 to 3 cycles for the
LxACK signal to reach the transmitter.
The links are designed to drive transmission lines with characteristic
impedances of 50Ω or greater. A higher transmission line impedance
reduces the on-chip effect of driver impedance variations, for distances
longer than about 6 inches. It is recommended that an external series
termination resistor be used at each link port pin to absorb reflections
from the open circuit at the destination. The external resistor should be
selected such that its value (plus the internal resistance of the driver)
be equal to the characteristic impedance of the transmission line.
Thus, if the typical internal drive resistance is 10Ω and the
characteristic impedance is 50Ω, then the link port pin resistor should
be 40Ω.
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