Table 10.4 Stctlx Transmit Control Register Bits - Analog Devices ADSP-2106x SHARC User Manual

The TXS status bits indicate whether the TX buffer is full (11), empty
(00), or partially full (10). To test for space in TX, therefore, test for
TXS0 (bit 30) equal to zero. To test for the presence of any data in TX,
test for TXS1 (bit 31) equal to one.
Bit(s) Name Definition
0 SPEN* SPORT Enable
1-2 DTYPE Data Type (data format, companding)
3 SENDN Serial Word Endian (1=LSB first)
4-8 SLEN Serial Word Length – 1
9 PACK Data Word Unpacking (32-bit to 16-bit)
10 ICLK* Internally Generated Transmit Clock
11 – reserved
12 CKRE Data, Frame Sync Sampling on Clock Rising Edge
13 TFSR* Transmit Frame Sync Required
14 ITFS* Internally Generated TFS
15 DITFS Data-Independent TFS
16 LTFS Active Low TFS
17 LAFS* Late TFS
18 SDEN SPORT Transmit DMA Enable
19 SCHEN SPORT Transmit DMA Chaining Enable
20-23 MFD Multichannel Frame Delay
24-28 CHNL** Current Channel Status (read-only)
29 TUVF** Transmit Underflow Status (sticky, read-only)
30-31 TXS** TX Buffer Status (read-only)
11=full, 00=empty, 10=partially full

Table 10.4 STCTLx Transmit Control Register Bits

* Must be set to 0 for multichannel operation.
** Status bits are read-only. They are cleared by disabling the serial port (setting
SPEN=0). TXS may subsequently change state if the data is read or written by the
ADSP-2106x core while the SPORT is disabled.
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Serial Ports 10
10 – 9