Analog Devices ADSP-2106x SHARC User Manual page 640

E Control/Status Registers
01=First stage of all packing and unpacking modes.
10=Second stage of 16-to-48 bit packing/unpacking or 32-to-48 bit
packing/unpacking
E.11 EXTERNAL MEMORY WAIT STATE CONTROL (WAIT)
The WAIT register is used to set up external memory wait states and
response to the ACK signal. WAIT is memory-mapped in internal
memory at address 0x0002. The WAIT register is initialized to
0x21AD 6B5A after a processor reset; this configures the ADSP-2106x
for 1) no idle state on PAGE boundary crossings, 2) six internal wait
states, 3) dependence on ACK for all memory banks and for unbanked
memory, and 4) multiprocessor memory space wait state enabled.
Bit Name
0-1 EB0WM
2-4 EB0WS
5-6 EB1WM
7-9 EB1WS
10-11 EB2WM
12-14 EB2WS
15-16 EB3WM
17-19 EB3WS
20-21 UBWM
22-24 UBWS
25-27 PAGSZ
28 PAGEIS
29 MMSWS Single wait state for Multiprocessor Memory Space access
30 HIDMA
31
* Unbanked memory wait states and wait state mode are applied to BMS -asserted
accesses.
Wait State Mode
EBxWM Wait State Mode
00 External acknowledge only (ACK)
01 Internal wait states only
10 Both internal and external acknowledge required
11 Either internal or external acknowledge sufficient
E – 32
www.BDTIC.com/ADI
Definition
External Bank 0 wait state mode
External Bank 0 number of wait states
External Bank 1 wait state mode
External Bank 1 number of wait states
External Bank 2 wait state mode
External Bank 2 number of wait states
External Bank 3 wait state mode
External Bank 3 number of wait states
Unbanked memory wait state mode*
Unbanked memory number of wait states*
Page size for DRAM (only in Bank 0)
Single idle cycle on DRAM page boundary crossing
Single idle cycle for DMA handshake
reserved