Eprom Booting - Analog Devices ADSP-2106x SHARC User Manual

host boot mode or no boot mode. In EPROM boot mode,
deasserted when the ADSP-2106x is not the bus master.
Note that when using any of the power-up booting modes, address
0x0002 0004 should not contain a valid instruction since it is not
executed during the booting sequence. A NOP or IDLE instruction
should be placed at this location.
11.6.2

EPROM Booting

EPROM booting through the external port is selected when the EBOOT
input is high. The byte-wide boot EPROM must be connected to data
bus pins 23-16 (DATA
23-16
ADSP-2106x should be connected to the EPROM's address lines. The
EPROM's chip select should be connected to
enable should be connected to
In a multiprocessor system, the
ADSP-2106x bus master. This allows wire-ORing of multiple
signals for a single common boot EPROM.
You can boot any number of ADSP-2106x's from a single EPROM,
using the same code for each processor or differing code for each.
During reset, the ADSP-2106x's ACK line is internally pulled high with
a 2 kΩ equivalent resistor and is held high with an internal keeper
latch. It is not necessary to use an external pullup resistor on the ACK
line during booting or at any other time.
11.6.2.1 Bootstrapping (256 Instructions)
When EPROM boot mode is configured, the External Port DMA
Channel 6 (DMAC6) becomes active following reset; it is initialized to
0x02A1, which allows external port DMA enable and selects DTYPE
for instruction words. The packing mode bits (PMODE) are ignored,
and 8-to-48 bit packing is forced with least-significant-word first.
The UBWS and UBWM fields of the WAIT register are initialized to
generate six wait states (seven cycles total) for the EPROM access in
unbanked external memory space. (Note that wait states defined for
unbanked memory are applied to
The UBWM field's initial value selects internal wait and external
acknowledge. Initially, the SHARC asserts acknowledge (high), but (if
another device drives acknowledge low during EPROM boot) the
www.BDTIC.com/ADI
System Design
). The lowest address pins of the
BMS
and its output
RD
.
BMS
output is only driven by the
BMS
-asserted accesses.)
11
BMS
is
BMS
11 – 29