Link Buffers - Analog Devices ADSP-2106x SHARC User Manual

To allow a transmitter and a receiver to be enabled (assigned and link
buffer enabled) at different times, LxACK, LxCLK, and LxDAT
be held low with the 50 kΩ internal pulldown resistors if LPDRD is
cleared when the link port is disabled. Thus, if the transmitter is
enabled before the receiver, LxACK will be low and the transmission is
held off. Similarly, if the receiver is enabled before the transmitter,
LxCLK will be held low and the receiver will be held off. If many link
ports are bused together, one external resistor should be used to pull
down each bused line instead of the internal pulldowns. This will
guarantee that the bused lines are not pulled down too strongly.
LxACK, LxCLK, and LxDAT
external pulldown resistors or the internal pulldowns are used.
9.4

LINK BUFFERS

Each link buffer consists of an external and an internal register (see
Figure 9.1). When transmitting, the internal register is used to accept
the DMA data from internal memory. The external register performs
the unpacking for the link port, most significant nibble first. These two
registers form a two-stage FIFO, the LBUFx buffer. Two words can be
written into the register (by DMA or from the core) before it signals a
full condition. As each word is unpacked and transmitted, the next
location in the FIFO becomes available and a new DMA request is
made. If the register becomes empty, the LxCLK signal will be
deasserted.
Full/empty status for the link buffer FIFOs is given by the LxSTAT bits
of the LCOM register. This status is cleared for a link buffer when its
LxEN enable bit is cleared in the LCTL register.
During receiving, the external buffer is used to pack the receive port
data (most significant nibble first) and pass it to the internal register
before DMA-transferring it to internal memory. This buffer is a two-
deep FIFO. If the ADSP-2106x's DMA controller does not service it
before both locations are filled, then the LxACK signal will be
deasserted.
The link buffer width may be selected to be either 32 or 48 bits. This
selection is made individually for each buffer with the LEXT bits in the
LCTL register. For 40-bit extended precision data or 48-bit instruction
transfers, the width must be set to 48 bits.
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Link Ports
should not be left unconnected unless
3-0
9
may
3-0
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