Analog Devices ADSP-2106x SHARC User Manual page 20

Contents
Figure 5.11 Short Word Addresses ..........................................................................5-28
Figure 5.12 Preprocessing of 16-Bit Short Word Addresses...................................5-29
Figure 5.13 48-Bit Words & 32-Bit Words Mixed In A Memory Block
(ADSP-21060) .......................................................................................5-31
Figure 5.14 48-Bit Words & 32-Bit Words Mixed In A Memory Block
(ADSP-21062 or ADSP-21061).............................................................5-32
Figure 5.a External Port Data Alignment ................................................................5-35
Figure 5.15 WAIT Register .......................................................................................5-42
Figure 5.16 Bus Idle Cycle, Hold Time Cycle, Page Idle Cycle...............................5-43
Figure 5.17 Example DRAM Interface......................................................................5-46
Figure 5.18 External Memory Access Timing...........................................................5-49
Figure 5.19 Multiprocessor Memory Access Timing ................................................5-51
Figure 6.1 ADSP-2106x Block Diagram ...................................................................6-2
Figure 6.2 DMA Data Paths & Control .....................................................................6-3
Figure 6.3 DMACx Registers ....................................................................................6-9
Figure 6.4 DMA Address Generation .....................................................................6-24
Figure 6.5 Rotating Priority Example (ADSP-21060 & ADSP-21062) ....................6-27
Figure 6.6 Chain Pointer Register & PCI Bit ..........................................................6-29
Figure 6.7 TCB Setup In Memory (For External Port DMA Channel).....................6-31
Figure 6.8 DMA Handshake Timing With Asynchronous Requests .......................6-45
DMAR
Figure 6.9 x Delay After Enabling Handshake DMA ....................................6-47
Figure 6.10 System Configurations For ADSP-2106x-To-ADSP-2106x DMA .........6-49
Figure 6.11 Example DMA Hardware Interface........................................................6-50
Figure 6.12 DMARx/DMAGx Timing ........................................................................6-51
Figure 7.1 ADSP-2106x Multiprocessor System ......................................................7-2
Figure 7.2 Data Flow Multiprocessing ......................................................................7-4
Figure 7.3 Cluster Multiprocessing ...........................................................................7-5
Figure 7.4 Two-Dimensional SIMD Mesh Multiprocessing.......................................7-8
Figure 7.5 Bus Arbitration Timing ...........................................................................7-12
Figure 7.6 Bus Request & Read/Write Timing .......................................................7-13
Figure 7.7 Core Priority Access Timing ..................................................................7-18
Figure 7.8 Broadcast Write Timing Example ..........................................................7-24
Figure 7.9 SYSTAT Register ..................................................................................7-35
Figure 8.1 External Port & Host Interface.................................................................8-2
Figure 8.2 Example Timing For Bus Acquisition ......................................................8-7
Figure 8.3 Example Timing For Host Read & Write Cycles ...................................8-11
Figure 8.4 SYSCON Register .................................................................................8-22
Figure 8.a External Port Data Alignment ................................................................8-26
Figure 8.5 Example Timing For Host Interface Data Packing ................................8-27
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