Analog Devices ADSP-2106x SHARC User Manual page 631

Control/Status Registers
IRPTL & IMASK
SFT3I
User Software Interrupt 3
SFT2I
User Software Interrupt 2
SFT1I
User Software Interrupt 1
SFT0I
User Software Interrupt 0
FLTII
Floating-Point Invalid Operation
FLTUI
Floating-Point Underflow
FLTOI
Floating-Point Overflow
FIXI
Fixed-Point Overflow
LP3I
Link Buffer 3 DMA
LP2I
Link Buffer 2 DMA
SPT1I
SPORT1 Transmit (or Link Buffer 1) DMA
SPT0I
SPORT0 Transmit DMA
SPR1I
SPORT1 Receive (or Link Buffer 0) DMA
SPR0I
SPORT0 Receive DMA
Default values for IMASK only; IRPTL is cleared after reset.
For IMASK: 1=unmasked (enabled), 0=masked (disabled)
All control and status bits are active high unless otherwise
noted. Default bit values after reset are shown; if no value
is shown, the bit is undefined at reset or depends upon
processor inputs. Reserved bits are shown with a gray
background. Reserved bits should always be written with zeros.
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31 30 29 28 27 26 25 24 23
0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7
0 0 0 0 0 0 0 0 0
22 21 20 19 18 17 16
0 0 0 0 0 0 0
EP0I
Ext. Port Buffer 0 (or Link Buffer 4) DMA
EP1I
Ext. Port Buffer 1 (or Link Buffer 5) DMA
EP2I
Ext. Port Buffer 2 DMA
EP3I
Ext. Port Buffer 3 DMA
LSRQI
Link Port Service Request
CB7I
DAG1 Circular Buffer 7 Overflow
CB15I
DAG2 Circular Buffer 15 Overflow
TMZLI
Timer Expired (Low Priority)
6 5 4 3 2 1 0
0 0 0 0 0 1 1
RSTI
RESET (non-maskable, read-only)
SOVFI
Stack Full/Overflow
TMZHI
Timer Expired (High Priority)
VIRPTI
Multiprocessor Vector Interrupt
IRQ2I
IRQ2 Asserted
IRQ1I
IRQ1 Asserted
IRQ0I
IRQ0 Asserted
E
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