System Design Example: Local Dram Interface - Analog Devices ADSP-2106x SHARC User Manual

9.10

SYSTEM DESIGN EXAMPLE: LOCAL DRAM INTERFACE

The example shown in Figure 9.8 shows how a multiprocessing system
can use link ports to connect to local memories and I/O devices. An
ASIC implements the interface between the link port and DRAM or an
I/O device. This minimal hardware solution frees the ADSP-2106x's
external bus for other shared-bus communication. The DRAM and
ASIC may be implemented on a single 10-pin SIMM module.
Accesses to the DRAM via a link is most efficient under DMA control.
The ASIC receives DMA control information from the link port and
sets up the access to the DRAM. It unpacks 16-bit data words from the
DRAM or packs 4-bit nibbles from the link. At the end of the DMA
transfer, an interrupt will allow the ADSP-2106x to send new control
information to the ASIC. The ASIC always reverts to receive mode at
the end of a transfer. The LxACK signal is deasserted by the ASIC
whenever a page change, memory refresh cycle, or any other access to
the DRAM occurs.
Memory modules may be shared by multiple ADSP-2106xs when the
link port is bused. Each link port supports 40 Mbyte access throughput
for either instructions or data. The ASIC is responsible for generating
the 2X clock when transmitting to the ADSP-2106x. The ASIC is also
responsible for generating sequential DMA addresses based on a start
address and word count.
DRAM 0
Link Interface
20 MHz Cycle
ASIC
16
Data
Address
&
Control Clk
DRAM 1
Link Interface
20 MHz Cycle
ASIC
16
Data
Address
&
Control Clk
Figure 9.8 Local DRAM With Link Ports
www.BDTIC.com/ADI
Link Ports
ADSP-2106x
L0DAT 3-0
L0CLK
L0ACK
6
Link Port 0
Link Port 1
ADSP-2106x
L1DAT 3-0
L1CLK
Link Port 0
L1ACK
6
Link Port 1
9
I/O Device
External
External
Port
Memory
DMA Device
External
Port
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Host