Figure 1.3 Adsp-2106X System - Analog Devices ADSP-2106x SHARC User Manual

1 Introduction
This manual covers three ADSP-2106x processors: the ADSP-21060,
ADSP-21062, and ADSP-21061. The ADSP-21060 contains 4 megabits of on-
chip SRAM, the ADSP-21062 contains 2 megabits, and the ADSP-21061
contains 1 megabit. The Memory chapter of this manual describes the
differences in memory architecture and programming considerations of the
three processors. All three processors are code- and function-compatible
with the ADSP-21020 processor. With the exception of memory size, the
ADSP-21060 and ADSP-21062 are identical in all other aspects as well.
Besides memory size, there are four differences between these two
processors and the ADSP-21061:
• No link ports on the ADSP-21061
• 6 DMA channels — 4 for serial port and 2 for external port (instead of 4)
• Additional features and changes in DMA for the serial port
• New idle 16 instruction for a further reduced power mode
These differences are described in detail in the DMA, Serial Port, and
Program Sequencer chapters.
1x CLOCK CLKIN
EBOOT
LBOOT
3
IRQ
4
FLAG
TIMEXP
LxCLK
LINK DEVICES
LxACK
(6 Maximum)
LxDAT
(OPTIONAL)
TCLK0
SERIAL
RCLK0
DEVICE
TFS0
(OPTIONAL)
RFS0
DT0
DR0
TCLK1
SERIAL
RCLK1
DEVICE
TFS1
(OPTIONAL)
RFS1
DT1
DR1
RPBA
ID
2-0

Figure 1.3 ADSP-2106x System

1 – 4
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ADSP-2106x
BMS
2-0
3-0
ADDR
31-0
DATA
47-0
RD
3-0
WR
ACK
MS
3-0
PAGE
SBTS
SW
ADRCLK
DMAR
1-2
DMAG
1-2
CS
HBR
HBG
REDY
BR
1-6
CPA
RESET JTAG
7
CS
BOOT
ADDR
EPROM
(OPTIONAL)
DATA
ADDR
DATA
MEMORY &
PERIPHERALS
OE
(OPTIONAL)
WE
ACK
CS
DMA DEVICE
(OPTIONAL)
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA