Interrupts For Single-Word Transfers - Analog Devices ADSP-2106x SHARC User Manual

Each EPBx buffer can be flushed (i.e. cleared) by writing a 1 to the
FLSH bit in the corresponding DMACx control register. This bit is not
latched internally and will always be read as a 0. Status can change in
the following cycle. An EPBx buffer should not be enabled and flushed
in the same cycle.
If packing and unpacking of individual data words is desired, the
packing mode must be selected in the PMODE bits of the EPBx buffer
control registers (DMAC6, DMAC7, DMAC8, and DMAC9). Either
16-to-32, 16-to-48, or 32-to-48 bit packing/unpacking can be selected.
The external host bus width indicated by the host packing mode bits
(HPM) in SYSCON must correspond to the external word width
selected by the PMODE bits.
If any of the three packing modes are used for single-word transfers,
the TRAN bit must also be appropriately set in the DMACx control
register. Set TRAN=1 for host reads from the EPBx buffer, or set
TRAN=0 for host writes to the EPBx buffer.
Note: To perform single-word, non-DMA transfers through the EPBx
buffers, the DMA enable bit (DEN) must be cleared in the appropriate
DMACx control register.

8.4.1.1 Interrupts For Single-Word Transfers

The interrupts for the four external port DMA channels can be used to
control single-word data transfers between the host and the
ADSP-2106x core. To do this, the DMACx control register must have
the following bit settings: DEN=0 and INTIO=1. This disables DMA
(DEN=0) and enables interrupt-driven I/O (INTIO=1). See the
DMA chapter or Control/Status Registers appendix of this manual for a
complete description of the DMACx control registers.
In this case the interrupt is generated whenever data becomes available
in the read port of the EPBx buffer, or whenever the write port does
not have new data to transmit. The EPBx buffer can then be read or
written by either the ADSP-2106x core or by an external device such as
the host. Generating interrupts in this fashion is useful for
implementing interrupt-driven I/O controlled by the ADSP-2106x core
processor.
This interrupt may be masked out (i.e. disabled) in the IMASK register.
If the interrupt is later enabled in IMASK, the corresponding IRPTL
latch bit must be cleared to clear any interrupt request that may have
occurred.
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