Analog Devices ADSP-2106x SHARC User Manual page 658

E Control/Status Registers
STCTL0
STCTL1
RXS
RX Data Buffer Status (read-only)
11=full, 00=empty, 10=partially full
ROVF
Receive Overflow Status (sticky, read-only)
NCH
Number of Channels – 1
MCE
Multichannel Enable
1=enable, 0=disable
SPL*
SPORT Loopback
1=enable, 0=disable
IRFS
Internally Generated RFS
1=internal RFS, 0=external RFS
RFSR*
Receive Frame Sync Required
1=RFS required, 0=RFS not required
CKRE
Clock Edge for Data, Frame Sync Sampling
1=rising edge, 0=falling edge
DTYPE: Normal Operation (Non-Multichannel)
DTYPE Data Formatting
00 Right-justify, zero-fill unused MSBs
01 Right-justify, sign-extend into unused MSBs
Compand using µ-law
10
11 Compand using A-law
All control and status bits are active high unless otherwise
noted. Default bit values after reset are shown; if no value
is shown, the bit is undefined at reset or depends upon
processor inputs. Reserved bits are shown with a gray
background. Reserved bits should always be written with zeros.
E – 50
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7
0 0 0 0 0 0 0 0 0
* Must be cleared for multichannel operation.
16
0 0 0 0 0 0 0
LRFS
Active Low RFS
1=active low, 0=active high
LAFS*
Late RFS
1=late RFS, 0=early RFS
SDEN
SPORT Receive DMA Enable
1=enable DMA, 0=disable DMA
SCHEN
SPORT Receive DMA Chaining Enable
1=enable chaining, 0=disable chaining
D2DMA*
2-Dimensional DMA Array Enable
6 5 4 3 2 1 0
0 0 0 0 0 0 0
SPEN*
SPORT Enable
1=enable, 0=disable
DTYPE
Data Type
SENDN
Serial Word Endian
0=MSB-first, 1=LSB-first
SLEN
Serial Word Length – 1
PACK
16-bit to 32-bit Word Packing
1=packing, 0=no packing
ICLK
Internally Generated Receive Clock
1=internal clock, 0=external clock
DTYPE: Multichannel Operation
DTYPE Data Formatting
x0 Right-justify, zero-fill unused MSBs
x1 Right-justify, sign-extend into unused MSBs
Compand using µ-law
0x
1x Compand using A-law
0x00E0
0x00F0