Two-Dimensional Dma - Analog Devices ADSP-2106x SHARC User Manual

6 DMA
6.6

TWO-DIMENSIONAL DMA

This section describes the changes in functionality that occur when the
ADSP-21060 or ADSP-21062 is placed in two-dimensional DMA mode.
(Note that two-dimensional DMA mode does not apply to the ADSP-
21061.) 2-D DMA mode is enabled by the L2DDMA bit in the LCOM
control register and the D2DMA bit in the SRCTL0 and SRCTL1
registers. If a particular mode of operation is not explicitly mentioned
below, then it is unchanged in 2-D mode.
6.6.1 2-D DMA Channel Organization
In 2-D mode, two-dimensional DMA array addressing can be
performed for the link buffers and serial ports. DMA channels 0-5
support 2-D DMA. Link buffers 4 and 5 (DMA channels 6 and 7) do
not support 2-D DMA. Table 6.16 shows the 2-D registers and their
mapping into the DMA channel registers. For the purpose of
discussion here, the 2-D array is addressed in row-major order.
2-D
Function
Index (address)
X Increment
X Count
Next Pointer
Y Increment
Y Count
X Initial Count
Table 6.16 2-D Register Mapping
In Table 6.16 the DMA channel number, x, is distinguished from the
standard numbering of serial ports and link ports as follows:
Transmit Link Buffer – Uses DMA Channel 5
Receive Link Buffer
Transmit SPORT
Receive SPORT
The Index register (II) is loaded with the first address in the data array and
maintains the current address by subtracting the X increment after each
transfer. The X Increment register (IM) contains the offset added to the
current address to point to the next element in the X dimension (next
column). The X Initial Count register (DA) contains the number of data
6 – 52
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DMA
Channel
Register
IIx
IMx
Cx
CPx
DBx
GPx
DAx (not part of chain; loaded by Cx)
– Uses DMA Channel 4
– Uses DMA Channel 3 or 1
– Uses DMA Channel 2 or 0