Analog Devices ADSP-2106x SHARC User Manual page 681

For example:
20118 LCNTR=10;
20119 jump my(db); 2012C my:
2011A do my until LCE;
2011B my: r0=r0+r1;
2011C r2=r2+r3;
2011D r1=r1+r2;
In the example, there is a loop inside a delayed branch. Because the
loop executes the instructions inside the loop ten times, the address
of the destination of the jump (
of going to label
sequential instruction at address
sequential execution. This is the reason why loop is restricted
inside the delayed branch.
• IDLE instruction
To come out of the idle instruction, an interrupt is needed. If the
user puts an IDLE instruction inside the delayed branch, the pro-
cessor is always in the idle state, unless there is an interrupt, hence
this instruction is restricted.
Chapter: 3 Page: 21
Revision Needed:
In the third paragraph, third sentence, the segment "8-instruction
intervals" should be replaced with "4-instruction intervals."
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DOCUMENTATION ERRATA
2012C
( ), the processor executes the next
my 2012C
2011C
) is flushed. After that, instead
and then continues the
H-5