External Memory Write – Bus Master - Analog Devices ADSP-2106x SHARC User Manual

CLOCK
ADDRESS
MSx , SW
RD or WR
DATA
ACK
Figure 5.18 External Memory Access Timing
Note that if a memory read is part of a conditional instruction that is not
executed because the condition is false, the ADSP-2106x still drives the
address and memory select for the read, but does not assert the read
strobe or read any data.
5.5.1.2 External Memory Write – Bus Master
External memory writes occur with the following sequence of events
(refer again to Figure 5.18):
1. The ADSP-2106x drives the write address and asserts a memory select
signal to indicate the selected bank. A memory select signal is not
deasserted between successive accesses of the same memory bank.
2. The ADSP-2106x asserts the write strobe and drives the data (unless
the memory access is aborted because of a conditional instruction).
Read Address / Write Address
www.BDTIC.com/ADI
Memory
Read Data / Write Data
5
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