Figure 1.1 Super Harvard Architecture - Analog Devices ADSP-2106x SHARC User Manual

1 Introduction
Figure 1.2 also shows the three on-chip buses of the ADSP-2106x:
the PM bus (program memory), DM bus (data memory), and I/O bus.
The PM bus is used to access either instructions or data. During a
single cycle the processor can access two data operands, one over the
PM bus and one over the DM bus, an instruction (from the cache), and
perform a DMA transfer.
The ADSP-2106x's external port provides the processor's interface to
external memory, memory-mapped I/O, a host processor, and
additional multiprocessing ADSP-2106xs. The external port performs
internal and external bus arbitration as well as supplying control
signals to shared, global memory and I/O devices.
Figure 1.3 illustrates a typical single-processor system. A
multiprocessor system is shown in Chapter 7, Multiprocessing.
Numeric Processor

Figure 1.1 Super Harvard Architecture

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Dual-Ported,
Multi-Access
Memory
Parallel
System
Crossbar Bus
Interconnect
I/O Processor
&
DMA Controller
Bus
Port