Figure 5.19 Multiprocessor Memory Access Timing - Analog Devices ADSP-2106x SHARC User Manual

Clock Cycles
ADDRESS
Write Address
SW
WR
RD
ACK
(Output by slave,
Input to master)
DATA
Write Data
ADSP-2106x
Master
Bus Master
Write
Slave
ADSP-2106x
accepts
Slave
data deasserts ACK
Multiprocessor
Write
(no wait states)

Figure 5.19 Multiprocessor Memory Access Timing

Note—Minimum access time is: 1 wait state (2 cycles) for IOP register reads
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Write Address
Slave holds ACK
low for 1 cycle
Write Data
Master Master
Write waits for
ACK
Slave has Slave
1 wait state, accepts
data
Multiprocessor
Write
(1 wait state)
3 wait states (4 cycles) for memory reads
Memory
Read Address
Slave holds ACK
low for 2 cycles
Master Master
Read waits for
ACK
Slave has
2 wait states,
deasserts ACK
Multiprocessor
Read
(2 wait states)
5
Read Data
Master
accepts
data
Slave
outputs
data
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