Asynchronous Transfer Timing - Analog Devices ADSP-2106x SHARC User Manual

8 Host Interface

8.2.2.1 Asynchronous Transfer Timing

When a ADSP-2106x's
ADSP-2106x immediately deasserts the REDY signal, with a delay of
approximately 10 ns. Refer to the ADSP-2106x Data Sheet for timing
exact specifications. (The REDY deassertion is activated from
RD
not from or
may not yet be enabled if
asserted before or after
reasserted until after
has been applied. This is true only if a
HBG
is asserted, otherwise it is determined by the t
characteristic specified in the "Multiprocessor Bus Request & Host Bus
Request" timing section of the ADSP-2106x Data Sheet.)
REDY is asserted prior to the
deasserted only if the ADSP-2106x is not ready for the read or write to
complete—the only exception is when
pin is an open-drain output to facilitate interfacing to common buses.
It can be changed to an active-drive output by setting the ADREDY bit
in the SYSCON register.
Figure 8.3 shows the timing of a host write cycle, discussed below,
including details of data packing and unpacking. This timing assumes
the use of the example host interface hardware shown in Figure 8.8 at
the end of this chapter.
1. The host asserts the address.
bus interface address comparator and need not be supplied directly
by the host. The selected ADSP-2106x deasserts REDY immediately.
2. The host asserts
requirements specified in the data sheet).
3. The selected ADSP-2106x asserts REDY when it is ready to accept
the data. This occurs after the current bus master has completed its
current transfer and has asserted
interface buffers to drive onto the ADSP-2106x bus.
4. The host deasserts
5. The selected ADSP-2106x latches data on the rising edge of
8 – 10
www.BDTIC.com/ADI
CS
chip select is asserted (low), the selected
WR
because the host interface buffers for
HBG
has not been asserted.
HBR
is asserted, but REDY will not be
HBG
has been asserted and a
RD
RD WR
or being asserted and becomes
CS
HBR
and
WR
and drives data (according to the timing
HBG
WR
when REDY is high and stops driving data.
CS
and
RD WR
and
CS
can be
RD WR
or strobe
WR
or strobe is active when
switching
TRDYHG
is first asserted. The REDY
CS
are decoded from the host
HBG
. enables the host
WR
.