Overview - Analog Devices ADSP-2106x SHARC User Manual

10.1

OVERVIEW

The ADSP-2106x has two independent, synchronous serial ports,
SPORT0 and SPORT1, that provide an I/O interface to a wide variety
of peripheral devices. Each serial port has its own set of control
registers and data buffers. With a range of clock and frame
synchronization options, the SPORTs allow a variety of serial
communication protocols and provide a glueless hardware interface to
many industry-standard data converters and CODECs.
The serial ports can operate at the full clock rate of the processor,
providing each with a maximum data rate of n Mbit/s, where n equals
the processor clock frequency. Independent transmit and receive
functions provide greater flexibility for serial communications. Serial
port data can be automatically transferred to and from on-chip
memory using DMA block transfers. Each of the serial ports offers a
TDM (time division multiplexed) multichannel mode.
Serial port clocks and frame syncs can be internally generated by the
ADSP-2106x or received from an external source. The serial ports can
operate with little-endian or big-endian transmission formats, with
word lengths selectable from 3 to 32 bits. They offer selectable
synchronization and transmit modes as well as optional µ-law or
A-law companding in hardware.
The serial ports offer the following features and capabilities:
• Independent transmit and receive functions.
• Can transfer data words up to 32 bits in length, either MSB-first or LSB-first.
• Double-buffering of data—both receive and transmit functions have a
data buffer register as well as a shift register; the double-buffering
provides additional time to service the SPORT.
• A-law and µ-law hardware companding on transmitted and received
words.
• Serial clock and frame sync signals can be generated internally, in a
wide range of frequencies, or input from an external source.
• Interrupt-driven, single-word transfers to and from on-chip memory
controlled by the ADSP-2106x core.
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Serial Ports 10
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