E.10 System Status (Systat) - Analog Devices ADSP-2106x SHARC User Manual

Control/Status Registers
Note: The setting of EPBR is not related to the CPA pin function
(core priority access).
(Additional Details: The ADSP-2106x has three on-chip buses that
are multiplexed at the external port: the PM bus (instructions or
data), DM bus (data), and I/O bus (DMA data). The PM bus and
DM bus are controlled by the ADSP-2106x processor core. The
I/O bus is controlled by the on-chip I/O processor. The I/O bus
connects the external port's DMA buffers to the ADSP-2106x's
internal memory and IOP registers.
Contention for use of the external bus occurs when both the
processor core and I/O processor attempt an off-chip read or
write during the same cycle. The contention occurs at the
ADSP-2106x's external port, where the three internal buses are
multiplexed together.
PM vs. DM bus conflicts are resolved with a fixed priority if the
accesses are both reads or both writes—the DM bus access occurs
first. An extra cycle is generated in the following cycle to allow
the PM bus access to occur.
For core processor priority, the I/O processor access will be
delayed until neither the PM bus nor DM bus is carrying an
access. For I/O bus priority, the PM and/or DM bus accesses
will be delayed until all pending I/O bus accesses are completed.)
Note: For even priority, if both the core and I/O processor try to
use the external bus continuously, they will each get a bus slot
every other cycle.
DCPR DMA Channel 6-9 Priority—Selects rotating or sequential priority
for DMA channels 6-9. When DCPR is set to 1, a rotating priority
scheme is implemented in which priority moves to the next
highest numbered channel (modulo 4). When DCPR is 0, highest
priority is assigned to channel 6 and lowest priority to channel 9.
1=Rotating priority
0=Sequential priority (ch6 high – ch9 low)
E.10 SYSTEM STATUS (SYSTAT)
The SYSTAT register provides status information, primarily for
multiprocessor systems. SYSTAT is memory-mapped in internal
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