Table 6.10 Dmastat Register - Analog Devices ADSP-2106x SHARC User Manual

Bit# Definition
0 DMA Channel 0 Status
1 DMA Channel 1 Status
2 DMA Channel 2 Status
3 DMA Channel 3 Status
4 DMA Channel 4 Status
5 DMA Channel 5 Status
6 DMA Channel 6 Status
7 DMA Channel 7 Status
8 DMA Channel 8 Status
9 DMA Channel 9 Status
10 DMA Channel 0 Chaining Status
11 DMA Channel 1 Chaining Status
12 DMA Channel 2 Chaining Status
13 DMA Channel 3 Chaining Status
14 DMA Channel 4 Chaining Status
15 DMA Channel 5 Chaining Status
16 DMA Channel 6 Chaining Status
17 DMA Channel 7 Chaining Status
18 DMA Channel 8 Chaining Status
19 DMA Channel 9 Chaining Status
20-31 reserved

Table 6.10 DMASTAT Register

1. Channel Status: 1 (active)=transferring data or waiting to transfer the current
block, and not transferring TCB. 0 (inactive)=DMA disabled, transfer complete, or
transferring TCB.
2. Channel Chaining Status: 1=transferring TCB or waiting to transfer TCB.
0=chaining disabled, or not transferring TCB.
3. Does not apply to the ADSP-21061.
Note 1: Status does not change on the master ADSP-2106x during external port DMA
until the external portion is completed (i.e., the EPBx buffers are emptied).
Note 2: If in chain insertion mode (DEN=0, CHEN=1), then channel chaining status
will never go to 1. Therefore, test channel status to see if it is ready so that your
program can rewrite the chain pointer (CPx register).
For a particular channel, the channel active status bit will be set if DMA
is enabled and the current DMA sequence has not completed. The
chaining status bit will be set if the channel is currently performing
chaining operations or if chaining is pending. There will be a single
cycle of latency between internal status changes and the update of the
DMASTAT register.
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1
1
1
1
1, 3
1, 3
1
1
1, 3
1, 3
2
2
2
2
2, 3
2, 3
2
2
2, 3
2, 3
DMA 6
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