Figure 3.16 Cache-Inefficient Code - Analog Devices ADSP-2106x SHARC User Manual

3 Program Sequencing
When a cache miss occurs, the needed instruction is loaded into the
cache so that if the same instruction is needed again, it will be there
(i.e. a cache hit will occur). However, if another instruction whose
address is mapped to the same set displaces this instruction, there will
be a cache miss instead. The LRU bits help to reduce this possibility
since at least two other instructions mapped to the same set must be
needed before an instruction is displaced. If three instructions mapped
to the same set are all needed repeatedly, cache efficiency (i.e. "hit
rate") can go to zero. The solution is to move one or more of the
instructions to a new address, one that is mapped to a different set.
An example of cache-inefficient code is shown in Figure 3.16. The
program memory data access at address 0x101 in the tight loop causes
the instruction at 0x103 to be cached (in set 3). Each time the
subroutine sub is called, the program memory data accesses at 0x201
and 0x211 displace this instruction by loading the instructions at 0x203
and 0x213 into set 3. If the subroutine is called only rarely during the
loop execution, the impact will be minimal. If the subroutine is called
frequently, the effect will be noticeable. If the execution of the loop is
time-critical, it would be advisable to move the subroutine up one
location (starting at 0x201), so that the two cached instructions end up
in set 4 instead of 3.
Address
0x0100
0x0101
0x0102
0x0103
0x0104
0x0105
0x0106 tight: f3=f3+f4;
0x0107
•
•
•
0x0200
sub:
0x0201
•
•
•
0x0211
•
•
•
0x021F
3 – 40

Figure 3.16 Cache-Inefficient Code

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lcntr=1024, do tight until lce;
r0=dm(i0,m0), pm(i8,m8)=f3;
r1=r0-r15;
if eq call (sub);
f2=float r1;
f3=f2*f2;
pm(i8,m8)=f3;
r1=R13;
r14=pm(i9,m9);
pm(i9,m9)=r12;
rts;