Shadow Write Fifo - Analog Devices ADSP-2106x SHARC User Manual

In most cases the ACK signal will be high and the ADSP-2106x slaves
will be ready to accept data at the start of the synchronous broadcast
write—the write completes in one cycle. If the ACK signal is low,
however, or one of the slaves is not ready to accept the data, the write
will take a minimum of three cycles.
When the wait state for multiprocessor memory space is enabled (with
the MMSWS bit of the WAIT register), the master ADSP-2106x will not
sample or drive ACK during the first two cycles of a synchronous
broadcast write. In this case the write will again take a minimum of
three cycles to complete.
(Note: The ADSP-2106x bus master enables a keeper latch on the ACK
line to prevent the signal from drifting. This eliminates any power
consumption caused by the signal drifting to the switching point and
improves the robustness of synchronous broadcast writes.
Multiprocessor systems that use synchronous broadcast writes should
keep the ACK line as free of noise as possible.)
8.3.4

Shadow Write FIFO

Because the ADSP-2106x's internal memory must operate at high
speeds, writes to the memory do not go directly into the memory
array, but rather to a two-deep FIFO called the shadow write FIFO.
When an internal memory write cycle occurs, data in the FIFO from
the previous write is loaded into memory and the new data goes into
the FIFO. This operation is normally transparent, since any reads of the
last two locations written are intercepted and routed to the FIFO.
There is only one case in which you need to be aware of the shadow
write FIFO: mixing 48-bit and 32-bit word accesses to the same
locations in memory.
The shadow FIFO cannot differentiate between the mapping of 48-bit
words and mapping of 32-bit words. (See Figures 5.8 and 5.9 in the
Memory chapter.) Thus if you write a 48-bit word to memory and then
try to read the data with a 32-bit word access, the shadow FIFO will
not intercept the read and incorrect data will be returned.
If 48-bit accesses and 32-bit accesses to the same locations absolutely
must be mixed in this way, you must flush out the shadow FIFO with
two dummy writes before attempting to read the data.
www.BDTIC.com/ADI
Host Interface 8
8 – 17