Figure 6.8 Dma Handshake Timing With Asynchronous Requests - Analog Devices ADSP-2106x SHARC User Manual

DMAR rising
edge allows 1st
DMAG to complete
CLK
1st DMA 2nd DMA
Request request
DMARx
DMAGx
DATA
47-0
Bus
Transition
Cycle
(If not bus
master)

Figure 6.8 DMA Handshake Timing With Asynchronous Requests

Notes:
DMARx
– DMA requests (
DMA request on the ADSP-2106x. When writing, data must be provided by the
DMAGx
device before
DMARx
hold asserted (low) until the data is available. When this happens, the
ADSP-2106x will attempt to service the request but will be delayed until the
rising edge.
– There is a minimum delay of three cycles before
transfer from the external DMA device to the ADSP-2106x (or to external memory)
occurs. However, the ADSP-2106x may not be able to issue a
several cycles after a DMA request if a higher priority DMA operation is requesting
service or if the bus is currently being used by another ADSP-2106x. Thus the
external DMA device must not assume that the grant will arrive within two cycles
unless higher priority DMA operations are disabled and the external bus is available
for the transfer.
– DMA requests are pipelined in the ADSP-2106x. The ADSP-2106x keeps track of up
to seven requests if it cannot service them immediately. It then services them on a
prioritized basis. The request tracking allows DMA transfers at up to the full clock
rate of the ADSP-2106x. The external DMA device is responsible for keeping track of
requests, monitoring grants, and pipelining the data when operating at full speed.
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DMAG has a wait state
because DMAR remained
asserted in the cycle prior
to the DMAG assertion
data valid
data valid
DMA device must place data in buffer prior
to DMAG falling edge if no wait state
) can be asynchronous. The
has been deasserted. If data is not available, the device may
DMAGx
DMA
DMA device need not provide
data until this cycle if wait state
DMARx
falling edge initiates a
DMARx
is asserted and the
DMAGx
grant for
6
data
data valid
valid
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