Analog Devices ADSP-2106x SHARC User Manual page 674

G SHARC Glossary
bus transition cycle (BTC)
host transition cycle (HTC)
asynchronous transfers
synchronous transfers
direct reads & writes
external port FIFO buffers
single-word data transfers
G – 2
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a cycle in which control of the external bus is
passed from one ADSP-2106x to another (in a
multiprocessor system)
a cycle in which control of the external bus is
passed from the ADSP-2106x to the host
processor—during this cycle the ADSP-2106x
RD WR
stops driving the , , ADDR
SW DMAG
ADRCLK, PAGE, , and
which must then be driven by the host
asynchronous host accesses of the ADSP-2106x;
after acquiring control of the ADSP-2106x's
external bus, the host must assert the
the ADSP-2106x it wants to access; the
ADSP-2106x uses the REDY output to add wait
states to an asynchronous access
synchronous host accesses of the ADSP-2106x;
CS
is not asserted and the host must act like
another ADSP-2106x in a multiprocessor
system, by generating an address in
multiprocessor memory space, asserting
RD
, and driving out or latching in the data; the
ADSP-2106x uses ACK to add wait states to a
synchronous access
a direct access of the ADSP-2106x's internal
memory or IOP registers by another
ADSP-2106x or by a host processor
EPB0, EPB1, EPB2, and EPB3—the IOP
registers used for external port DMA transfers
and single-word data transfers (from other
ADSP-2106xs or from a host processor); these
buffers are 6-deep FIFOs
reads and writes to the EPBx external port
buffers, performed externally by the
ADSP-2106x bus master or internally by the
ADSP-2106x slave's core; these occur when
DMA is disabled in the DMACx control
register
MS
, ,
31-0 3-0
x signals,
CS
pin of
WR
or